1. Field of the Invention
This invention generally relates to methods for inspecting a wafer and/or predicting one or more characteristics of a device being formed on a wafer.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as integrated circuits involves forming multiple layers on a wafer. Different structures are formed on different layers of the wafer, and some structures on different layers are intended to be electrically connected to each other while other structures on different layers are intended to be insulated from one another. If the structures on one layer are not properly aligned with other structures of other layers, the misalignment of the structures can prevent the proper electrical connection of some structures and/or the proper insulation for other structures. Therefore, measuring and controlling the alignment of multiple layers on a wafer is important in the successful manufacture of working semiconductor devices.
Generally, the alignment of one layer to another layer on a wafer is determined by the alignment of the wafer in an exposure step of a lithography process performed on the wafer. In particular, since the lithography process involves forming patterned features in a resist material that are then transferred to a device material using other fabrication processes, the lithography process generally controls where the patterned features (and therefore where device structures formed from the patterned features) are formed on the wafer. Therefore, measuring and controlling alignment of the wafer and thereby overlay of features on one layer with respect to features on another layer before, during, and/or after the lithography process is a critical step in the fabrication process.
Parameters of the lithography process other than overlay also affect the resulting patterned features formed on the wafer. For example, the focus and dose of the exposure tool used in the lithography process can affect various characteristics of the patterned features such as critical dimension, side wall angle, and height. If the patterned features are not formed within specifications for such characteristics, device structures formed from the patterned features may not be properly insulated from one another or properly connected with one another. In addition, such characteristics can also affect electrical characteristics of devices formed on the wafer. Therefore, it is important to monitor and control multiple parameters of the lithography process to ensure that working devices are fabricated and also to ensure that devices having suitable functionality are fabricated.
Accordingly, it would be advantageous to develop systems and/or methods that can be used to improve the devices fabricated on wafers by eliminating design problems before the devices are fabricated and monitoring and controlling the lithography process.